Usually, electronic systems such as computers and electronic control systems include a number of semiconductor integrated circuits which include a plurality of logic circuit blocks. Prior to or during the actual use of such systems, the logic circuit blocks may have to be tested as to whether they can perform their assigned logic functions. Hereinafter, such test is referred to as "logic test". When a number of circuit blocks have to be subjected to "logic tests", it will be disadvantageously necessary to use a large-scale computer for performing the logic tests, and programs for the tests should be complicated ones.
In order to solve such problems, integrated circuits which can be easily tested have been proposed. They include shift registers (or "scan-paths") therein, as shown in an article "APPLICATION OF SHIFT REGISTER APPROACH AND ITS EFFECTIVE IMPLEMENTATION" by M. Kawai et al in 1980 IEEE Test Conference Proceedings Paper 2.2, pages 22-25. The designing concept of such integrated circuits is based on modifying sequential circuitry into a combination of a plurality of smaller logic circuit blocks by means of shift registers, with such logic blocks being formed as being testable.
The use of such "scan-paths" has eliminated the aforementioned problems accompanying the logic tests of integrated circuits or even relatively large-scale integrated circuits. However, when this technique of dividing a sequential circuit into a plurality of smaller circuit blocks is employed, as the number of the divided logic circuit blocks increases, the number of clock signals for driving the scan-paths also increases, which, in turn, makes it necessary to increase the number of input terminals on the integrated circuit for the externally applied clock signals. This causes an integrated circuit package to become bulky, which may raise the cost of the integrated circuts. In some cases, it will be impossible to realize practical integrated circuits.
Accordingly, an object of the present invention is to eliminate the above-stated problem, by providing a novel semiconductor integrated circuit and a novel method of testing it, which can eliminate the need for increasing the number of the input terminals for receiving externally applied clock signals for use in testing circuit blocks, the number of which clock signals must be increased when the number of the circuit blocks increases.
Other objects, features and results of the present invention will become clear from the accompanying claims and the following detailed description of the invention.